The use of PLDs, such as CPLDs or FPGAs, is growing in mobile electronic devices. With shorter product development cycles, programmable logic devices provide advantages such as last minute hardware modifications and adaptability to changing product requirements. However, power consumption in programmable logic is sometimes greater than custom integrated circuits designed for mobile devices, for example. Higher power consumption in a mobile device, such as a cell phone, is a problem since battery life is limited.
FIG. 1 is an example of a conventional PLD 100. The PLD 100 includes a plurality of logic blocks (LBs) 110l to 110m coupled together through a global bus 130. Each logic block includes macrocells 120 or, in the case of a FPGA, logic elements (LEs). A plurality of clock signals 140 are fed through the global bus 130. The clock signals 140 are used by any logic, such as sequential logic or registers, in each macrocell which require clocking.
Higher power consumption in PLDs may occur because buffers, such as an inverter, are used for maintaining higher frequency clock speeds along a path connecting a clock signal(s) to a macrocell as clock signal distortion increases as the length of a wire increases. The layout of clock signals 140 connected to macrocell 120 is sometimes referred to as a clock-tree or a buffer-tree. Power consumption in the buffers along a clock path becomes greater as clock speeds increase. These buffers consume a large amount of power in the PLD since the clock signals are typically the highest frequency signals in the PLD. Higher frequency signals consume more power since the buffers toggle more frequently. There has been a trend towards increasing clock rates with the demands for more processing power on mobile devices. In a typical PLD 100, the macrocells used depend on the programming loaded from non-volatile memory during initialization of the chip which sets programmable switches within the chip. The switches can be transistors, such as complementary metal oxide semiconductor (CMOS) transistors. The switches determine which logic in the macrocell will be activated and can be electrically-erasable. Each switch may have a binary value of 0 or 1. Often, many of the clock signals 140 become unnecessary since not all of the macrocells require clocking. Therefore, a need exists for reducing power consumption in electronic devices without the limitations of the prior art.